The Night Shift: Overnight Tech News with Jennifer Hudsen • 4:30 a.m. edition • Cutoff August 27, 2026, 4:36 a.m. EDT / 08:36 UTC
Movandi Says Its New Clock Chips Cut Comparable-Jitter Power 10×—Independent Benchmarks Are Still Missing
Movandi announced two frequency-synthesizer chips that it says deliver 75 femtoseconds of total jitter while drawing 150 milliwatts, or one-tenth the power of existing products with comparable jitter. Those are company-supplied specifications in a launch release, not results independently reproduced by The IT Guys or an outside test lab.[1]
Featured image disclosure: original Jennifer Hudsen newsroom concept art created for The IT Guys. It is not a Movandi or TSMC product image, and its waveforms and chip diagrams are illustrative rather than measured test data.
What happened
Movandi introduced the MV3564 and MV3514 on August 27. The Business Wire release, accessible through Yahoo Finance, carries a publication timestamp of 07:01 UTC, or 3:01 a.m. Eastern. That places it inside this desk’s strict core window, which began at the prior Night Shift cutoff of 06:09:24 UTC and ended at 08:36:50 UTC.[1]
The company describes both parts as pin- and feature-compatible frequency synthesizers made on TSMC’s 40-nanometer radio-frequency CMOS process. Movandi says they integrate a voltage-controlled oscillator, multiple phase-locked loops, phase synchronization and an alignment engine. The stated aim is to give designers one clocking architecture that can serve wireless equipment, high-speed converters, AI-network links and power-constrained robots or drones.[1]
The two parts cover different frequency bands. Movandi lists the MV3564 at 4.3–8.7 GHz and 8.6–12.3 GHz, while the MV3514 covers 7.76–9.84 GHz and 12.33–14.34 GHz. It also claims deterministic phase re-synchronization, 30-bit fine phase adjustment, internal-crystal or external-reference support, and buffered reference-clock output.[1]
Availability is limited in an important way: Movandi says the devices are production sampling now and will be shown at LEAP 2026 in Riyadh from August 31 through September 3. Sampling is not the same as broad distributor inventory, high-volume production, qualification in a customer system or a published ship date for finished equipment.[1]
Why it matters
A frequency synthesizer is a clock source. In radios, converters and high-speed links, its timing stability affects how accurately the system can place a signal in frequency and sample data in time. Jitter is unwanted timing variation. At high data rates, very small errors can shrink signal margins, raise conversion noise or make synchronization between devices more difficult.
Power matters for a different reason. A synthesizer may be only one block in a base station, switch, accelerator tray or robot, but modern systems repeat clocking functions across many channels and boards. Lower power per clock can reduce heat, simplify cooling and preserve a tighter power budget for the components doing useful compute or radio work. Integration can also reduce board area and the number of external parts—if the integrated implementation meets the full system’s noise and reliability requirements.
Analysis: the most consequential part of Movandi’s announcement is not the AI label. It is the combination the company is claiming: very low timing jitter, 150 mW consumption, integrated oscillation and multi-chip phase control. If independently validated under realistic reference-clock, temperature, supply-noise and output-loading conditions, that package could help dense radios and clock trees. The release does not prove those system-level outcomes.
The “10× lower power” line needs careful reading. Movandi compares its parts with unspecified existing products offering comparable jitter performance. The release does not name the comparison set, test instruments, offset-frequency integration range, operating voltage, output configuration, environmental conditions or statistical spread. Without those details, readers can repeat the claim only as Movandi’s comparison—not as a universal market benchmark.[1]
Who is affected
Wireless equipment designers are the clearest audience. Movandi names customer-premises equipment, gNodeB base stations, O-RAN and backhaul, including emerging 6G work.[1] Data-center architects may care where precise clocks coordinate high-throughput scale-up or scale-out links. Converter-board teams may evaluate the parts beside high-speed ADCs and DACs. Robotics and drone teams may value lower power, but only after confirming shock, vibration, temperature, phase-noise and supply requirements for their specific hardware.
For ordinary PC, phone and small-business buyers, there is no immediate purchasing action. These are infrastructure components, not a new router or accelerator card. Any benefit would arrive later through equipment designed around them, and no finished consumer product was announced in the opened sources.[1]
What engineers and buyers should do
- Request the real datasheet and characterization package. Confirm how “75 fs total jitter” is integrated and measured, including frequency offsets, carrier frequency, output mode, reference source and test equipment.
- Reproduce the power comparison. Normalize supply rails, enabled outputs, frequency band, divider state and synchronization features. A headline milliwatt number may not describe every operating mode.
- Test the clock inside the target system. Measure phase noise, spurs, lock time, re-sync behavior and jitter with realistic power-supply noise, board layout, temperature and adjacent radios or high-speed digital devices.
- Verify sampling status. Ask for orderable part numbers, package options, sample lead times, qualification status, longevity commitments, minimum order quantities and the expected production ramp. Do not treat a trade-show demonstration as supply assurance.
- Model total board impact. Integrated VCO and alignment functions can remove parts, but compare the complete bill of materials, layout area, thermal path, firmware effort and failure modes—not only the synthesizer’s nominal draw.
- Keep a second source where continuity matters. Pin compatibility between two parts from one vendor provides frequency flexibility; it does not create supplier diversity.
Upside, cautions and unknowns
Potential upside: a genuinely lower-power low-jitter clock could make dense wireless and interconnect designs cooler and smaller. Integrated phase alignment could also reduce external clock-distribution complexity. Those benefits remain design possibilities until customer qualification or independent measurements show them in a real system.
Caution: the available evidence is a company launch release syndicated by several outlets. Syndication confirms what Movandi announced; it does not independently validate performance. TSMC North America’s CEO supplied a supportive quote in the release, but that quote is not a third-party benchmark of the finished devices.[1]
Unknown: the opened sources do not provide pricing, packages, detailed phase-noise plots, qualification grades, reference designs, customer names, production-volume dates, independent lab results or a public datasheet. They also do not establish that any commercial AI data center, 6G network, robot or drone has deployed either part.[1]
Claim map at the cutoff
| Claim surface | What is supported | What remains unproven |
|---|---|---|
| Timing and power | Movandi states 75 fs total jitter at 150 mW and a 10× power advantage versus unspecified comparable-jitter products.[1] | Independent reproduction, full methodology and universal superiority. |
| Integration | The company says VCO, multi-PLL synchronization and alignment functions are integrated.[1] | Actual board-area savings in a named customer design. |
| Manufacturing | Movandi identifies TSMC 40nm RF CMOS as the process.[1] | Yield, qualification status and production volume. |
| Availability | Movandi says production samples are available now and a LEAP demonstration is scheduled.[1] | Broad inventory, price, customer deployment or finished-product launch. |
Frequently asked questions
Did Movandi release a finished AI accelerator?
No. It announced frequency-synthesizer components intended to supply precise clocks for wireless and high-speed systems, including infrastructure used around AI workloads.[1]
Is the 10× power reduction independently verified?
Not in the sources opened for this report. It is Movandi’s comparison against unspecified existing products with comparable jitter.[1]
What does 75 femtoseconds mean?
A femtosecond is one quadrillionth of a second. The figure is Movandi’s stated total timing-jitter result; interpreting it properly requires the missing measurement bandwidth and operating conditions.[1]
Can buyers order the chips today?
Movandi says production samples are available. The release does not publish pricing, distributor stock or a high-volume production date.[1]
Why cover a small clock chip?
Large AI and wireless systems depend on less glamorous timing, power and interconnect components. A real efficiency improvement can matter when multiplied across dense hardware, but the validation burden should scale with the claim.
Sources
- Business Wire/Movandi: “Movandi Redefines Synthesizer PLL Efficiency, Delivering Peak Performance at Lower Power for Next-Gen Wireless and AI Infrastructure” — company announcement syndicated by Yahoo Finance, published August 27, 2026 at 07:01 UTC.
- FinancialContent syndication of the same Business Wire release — corroborates the distributed text but is not independent performance validation.
- Movandi official website — first-party company and technology context; not an independent benchmark.
Reporting cutoff: August 27, 2026, 4:36:50 a.m. EDT / 08:36:50 UTC. The announcement’s 07:01 UTC timestamp falls inside the strict core window beginning at the prior desk’s actual 06:09:24 UTC cutoff. This article covers one subject and was checked against The IT Guys’ daytime and earlier Night Shift coverage.